1. Field of Invention
The present invention relates to a data transmission sequencing method. More particularly, the present invention relates to a bridging device between data buses and a method for ensuring proper data transmission sequence.
2. Description of Related Art
In computer systems, a bridging device is a common piece of hardware. Various data buses are connected together by bridging devices so that data can be sent freely to various devices via the buses. For speeding up the data movement, the implement of posted write buffers are essential. Furthermore, to ensure transmission accuracy, data must be transmitted in proper sequence.
FIG. 1 is a sketch of a conventional bridging device and associated data buses. As shown in FIG. 1, the bridging device 180 of computer system is connected to at least one primary bus 100 and a secondary bus 110. A typical read/write cycle for this bridging device 180 includes a primary-to-secondary write operation 170 (PS_w), a primary-to-secondary read operation 150 (PS_r), a secondary-to-primary write operation 160 (SP_w) and a secondary-to-primary read operation 140 (SP_. In a conventional computer system, the bridging device uses a type of simple data transmission sequence to process data transfer. To process a read operation, the bridging device first checks if write data within write buffers 120 or 130 have already been transmitted. In other words, if a read operation is following a few write operations, the read operation can only be executed when all previous write data stored in the write buffer 120 or 130 have been transmitted.
FIG. 2 is a diagram showing the read/write cycles of the various buses connected to a conventional bridging device. As shown in FIGS. 1 and 2, when the secondary bus executes two write operations to transmit write data to the primary bus, a pair of posted write cycles SP_w[0] and SP_w[1] are issued on the secondary data bus. In the meantime, a primary bus to secondary bus data read request issues on the primary bus. Hence, a PS_r_a (address phase of PS_r) issues on the primary bus. To achieve proper data transmission sequence in a conventional bridging device, the bridging device suppresses subsequent actions of the secondary bus (in other words, SP_w or SP_r). Moreover, action of the PS_r must wait until all write data within posted write buffer 130 are sent to the primary bus. In other words, PS_r can be transmitted to the secondary data bus only after the posted write cycles SP_w[0] and SP_w[1] on the primary bus are issued. Consequently, the first idle time on the secondary bus can be seen.
When the read operation is transmitted to the secondary data bus, or in other words, timing the cycle PS_r is issued on the secondary bus, the second idle appears on the primary bus because the primary bus is waiting for the response data. When the bridging device transmits the response data (PS_r_d: data phase of PS_r) to the primary bus, the third idle time appears on the second bus because the secondary bus needs to wait for response data actually transmitted to the primary bus. Thereafter, secondary-to-primary bus write request is resumed. For example, posted write cycles SP_w[2] and SP_w[3] are issued on the secondary bus. In brief, this type of data transmission sequencing scheme leads to three major idle times resulting in a lowering of data transmission speed.